1. Field of the Invention
This invention relates to an address generator, more particularly to a low cost and highly efficient address generator for generating a plurality of addresses to be used in zig-zag scanning of the contents of a memory array.
2. Description of the Related Art
As VLSI technology advances, more and more computational power can be integrated on a single chip. Conventionally, a programmable or domain-specific processors, such as a DSP or VSP processor which is incorporated with a conventional address generator, was developed for audio or still image applications. For real-time video applications, an array of VSP processors are needed in order to meet computational requirements. To enhance computation capability, there is a need for the conventional address generator to have parallel data paths with multi-stage pipeline architecture. However, such a computational capability can only be demonstrated when data to be processed are scheduled in advance. Otherwise, idle or pipeline stall operations may be detected and hence, overall performance becomes degraded. Furthermore, the conventional address generator having parallel data paths with multi-stage pipeline architecture occupies a relatively large area of the chip so as to result in cost-inefficiency. Moreover, the conventional address generator can merely generate addresses to be used in only one of the different scanning methods, for example, zig-zag scanning, block scanning, transposed scanning, . . . , etc., available when scanning the contents of a memory array.